Load sequencer controller

ABSTRACT

A load sequencer controller is disclosed herein which serves to sequentially allocate and time a plurality of load intervals. The controller includes a plurality of interval time storage memories, each corresponding with an associated load interval to be timed. Each of the memories includes a plurality of electrically alterable and interrogatable bistable memory means which serve to store binary information. The weighted binary content of each memory is a decimal number representative of a desired time duration for an associated load interval. An interrogation circuit serves to sequentially apply interrogation signals to the memories so that when any one memory is interrogated the output of that memory provides a pattern of binary signals. An actuating circuit receives pulses from a source of equi-time-spaced pulses and serves to actuate the interrogation circuit each time the decimal number of the received pulses is equal to the decimal weight of the pattern of binary signals of the memory last interrogated.

United States Patent [72] Inventors Peter G. Bartlett 340/40 Bettendorf,Iowa; 3,375,494 3/1968 Piening etal. 340/40 Joseph Mesch" Lyons PrimaryExaminer-Terrell W. Fears [211 App]. No. 682,814 A M Tlb d Bod 221 FiledNov. 14, 1967 omey 1 my Y [45] Patented May 18, 1971 [73] Ass'gnee ilndusmes ABSTRACT: A load sequencer controller is disclosed herein W orwhich serves to sequentially allocate and time a plurality of loadintervals. The controller includes a plurality of interval 54 I LOADSEQUENCER CONTROLLER time storage memories, each corresponding with anassociated 31 Claims, 4 Drawing Figs load interval to be timed. Each ofthe memories includes a pluwhy of electrically alterable andinterrogatable bistable U.S. 173.2, memory means serve to storeinformation. The 340/ 35 weighted binary content of each memory is adecimal number [5]] [lit-Cl Gllc 11/22 representative of a desired timeduration for an agsgcialed 0f load intervaL An interrogation circuitserves to sequentially 173.2, (AM), 174 (CM), 35, 37, 40 41 applyinterrogation signals to the memories so that when any (lnqulred),92/2992/35, 92/50, 92/12, 146-2, one memory is interrogated the output ofthat memory pro- 3091, 343 vides a pattern of binary signals. Anactuating circuit receives pulses from a source of equi-time-spacedpulses and serves to [56] References and actuate the interrogationcircuit each time the decimal UNITED STATES PATENTS number of thereceived pulses is equal to the decimal weight 3,300,775 1/ I967 Dowling340/41X of the pattern of binary signals of the memory last inter-3,302,170 1/1967 Jensen et al. 340/40x rogated.

/C BINARY RES ETj S C O U N T E R 30 6 32 a i-b r-c d l- A BINARY 80 g N+60 S HAPER COM PARATOR I RI I l i i I i l FFI FF2IFl"-'3 FF4 RESET 3 nT I Is 5 INTERVAL TIME 9 E, E STORAGE CERAMIC A MEMORY MATRIX A2 1 A A4INTERVAL J Oio I 2 TIME 0 o 'l I SEQUENCER wR ITE I TW CIRC TM3JINTERROGATOR U T o o I I 3,305,828 2/1967 Auer,.lr.etal.

PATENIEU MAY is [an SHEET 2 OF 3 M W mam B. Y HWJIS RE m} MM 56. mt H 703) 56 BE; U% M PJ 5 5E3 m?) 56 NEE; m 6E 56 NE; {N3 .56 mEEs m; b6 BE;

ATTORNEYS LOAD SEQUENCER CONTROLLER This invention relates to the art ofelectrical controls and, more particularly, to electrical controls forsequentially allocating and timing a plurality of load intervals.

The invention is particularly applicable to the art of traffic controland will be described with particular reference thereto; although, it isto be appreciated that the invention has broader applications, such asin process control or other control arts, wherein means are required tosequentially allocate and time a plurality of load intervals.

In the past, load intervals have been sequentially allocated and timedwith the use of an electromechanical step switch mechanism, using breakaway cams to control the load sequencing program. Such electromechanicalmechanisms are inherently slow in operation, and any program changerequires the breaking away of a new set of cams. The reliability andflexibility of such an electromechanical mechanism is limited due to theuse of mechanical moving parts.

In more recent years, electronic trafi'rc controllers have included ringcounter and ring timer circuits for sequentially allocating varioustraffic intervals in a cyclical fashion. Such circuits, however, haveusually incorporated RC timers for timing the durations of the varioustraffic intervals. These timers are analog and, hence, the timings maybecome inaccurate due to variations in values of the circuit componentsupon temperature changes of the surrounding environments. Also, thesecircuits are not readily adjustable to provide for interval programchanges or interval timing changes.

The present invention is directed toward a load sequence controllerwhich sequentially allocates and times a plurality of load intervalswithout the use of electromechanical mechanisms and the like, andwherein readily adjustment may be made of the interval timing and/orinterval program.

In accordance with one aspect of the present invention, the apparatusfor sequentially allocating and timing a plurality of load intervalsinclude a plurality of interval time storage memories, eachcorresponding with an associated load interval to be timed, and whereineach memory includes a plurality of electrically alterable andelectrically interrogatable bistable memory means, such as ferroelectriccapacitor storage means, each storing a binary l or binary signal sothat the weighted binary content of a memory is a decimal numberrepresentative of a desired time duration for an associated loadinterval. Each of the memory means has an input for receiving aninterrogation signal and an output for carrying a binary signal inresponse to receipt of an interrogation signal. An interrogation meansserves to sequentially apply interrogation signals to the plurality ofmemories so that when any one memory is interrogated the outputs of itsplurality of memory means provide a pattern of binary signals. Also, anactuating means receives pulses from a source of equi-time-spaced pulsesfor actuating the interrogating means to interrogate the next succeedingof theplurality of memories when the decimal number of thepulsesreceived is equal to the decimal weight of the pattern of binarysignals on the outputs of the memory means of the memory lastinterrogated.

In accordance with a more limited aspect of the present invention, thereis also provided a plurality of interval program storage memories eachcorresponding with an associated load interval to be allocated, andwherein each of the memories correspond in structure with the memoriesin the interval time storage memories.

In accordance with another aspect of the present invention, there isprovided a new traffic controller which serves to sequentially allocateand time a plurality of traffic intervals to be displayed by trafficsignal light means and wherein the traftic controller comprises aplurality of trafi'ic interval time storage memories, one each for eachof the traffic intervals to be allocated and timed. Each of the trafiicinterval time storage memories includes a plurality of the abovedescribed electrically alterable and electrically interrogatablebistable memory means.

The primary object of the present invention is to provide an improvedsolid state load sequence controller which is relatively inexpensive tomanufacture and is relatively economical to operate.

Another primary object of the present invention is to provide animproved solid state load sequence controller which is relativelyinexpensive to manufacture and is relatively economical to operate.

Another object of the present invention is to provide a load sequencecontroller having electrically alterable and electrically interrogatableinterval time storage memories and/or interval program storage memories.

Another object of the present invention is to provide a load sequencecontroller having interval time and interval program storage memorieswhich incorporate ferroelectric storage capacitors.

A still further object of the invention is to provide an improvedtrafiic controller for sequentially allocating and timing trafiicintervals, wherein the interval timings and/or programs are electricallyalterable and interrogatable.

A still further object of the present invention is to provide animproved trafiic controller incorporating ferroelectric capacitorstorage elements.

These and other objects and advantages of the invention will becomeapparent from the following description of the preferred embodiments ofthe invention as read in connection with the accompanying drawings, inwhich: I

FIG. 1 is a combined schematic-block diagram illustration of oneembodiment of the invention;

FIG. 2 is a schematic illustration of a ceramic memory single bitdevice;

FIG. 3 is a schematic illustration of a ceramic memory matrix; and,

FIG. 4 is a combined schematic-block diagram illustration of a secondembodiment of the invention.

Referring now to the drawings, wherein the showings are for purposes ofillustrating the preferred embodiments of the invention, and not forpurposes of limiting same, FIG. 1 illus trates one embodiment of theinvention in the form of a variable time, fixed program, two phasetraffic controller. This controller serves to sequentially allocate andtime main street go and caution intervals and cross street go andcaution intervals. the controller generally comprises: a pulse source Sof equitime-spaced pulses; a binary counter C; a binary comparator BC; asequencer-interrogator I; an interval time storage memory matrix TM,having four word line memories TM], TM2, TM3 and TM4; a time writecircuit TW; and, a load'control circuit LC.

CERAMIC MEMORY DEVICE The ceramic memory matrix TM preferably takes theform as illustrated in out copending application, Ser. No. 640,717,filed May 23, I967, and assigned to the same assignee as the presentinvention, and which application is herein incorporated by reference toPat. No. 3,401 ,377 issued on said application. As disclosed in saidpatent, the matrix utilizes bistable memory means of the nondestructivereadout, dual plate type comprising an easily polarized memory plate anda permanently polarized drive plate having facing surfaces which aresecured to each other. The ceramic memory matrix disclosed thereincorporates several word lines each having several bits. Anunderstanding of the matrix may be best understood by first consideringthe construction of a single bit ceramic memory device. A single bitceramic memory device 10 is shown in FIG. 2, and generally comprises amemory plate 12 constructed of ferroelectric material, such as bariumtitanate, Rochelle salt, lead metaniobate or lead titanate zirconatecomposition, for example. In its preferred form, however, memory plate12 is constructed of lead titanate zirconate composition since it iseasy to polarize. Drive plate 14 is preferably constructed offerroelectric material having piezoelectric characteristics, such aslead titanate zirconate composition. However, the drive plate may beconstructed of any material that will change its dimensions uponapplication of an electrical signal, such as, for example,magnetostrictive material, which upon application of current theretowill undergo physical dimension changes. Drive plate 14 is permanentlypolarized and need not be constructed of easily polarizable material,such as lead titanate zirconate composition.

Plates l2 and 14 are, in their unstressed condition, approximately flat,and are oriented so as to be in substantial superimposed parallelrelationship. The upper surface of plate 12 is coated with anelectrically conductive layer 16, and the lower surface of plate 14 iscoated with an electrically conductive layer 18. Layers l6 and 18 may beof any suitable electrically conductive material, such as silver.lnterposed between facing surfaces of plates 12 and 14 there is provideda third layer 20 of electrically conductive material. Layer 20 may beconstructed of a conductive epoxy, such as epoxy silver solder, so thatfacing surfaces of plates 12 and 14 are electrically connected togetheras well as mechanically secured together. In this manner, as will bedescribed below, when drive plate 14 is stressed it, in turn, transmitsmechanical forces to plate 12, so as to mechanically stress plate 12 indirections acting both laterally and perpendicularly of its plane.

Drive plate I4 may be pemianently polarized by applying an electricfield across its opposing flat surfaces. Thus, as shown in FIG. 2, layer18 is electrically connected to a single pole, double throw switch S1which serves to connect layer I8 with either an electrical reference,such as ground, or to an interrogating readout voltage source V,,,.Similarly, layer 20 is connected with the single pole, double throwswitch S2. Switch S2 serves to connect layer 20 with either anelectrical reference, such as ground, or to a source of polarizingvoltage B+. Plate 14 may now be polarized by connecting layer 20 withthe B+ voltage supply source and layer 18 to ground potential. Thus, anelectrical field of sufiicient magnitude to polarize plate I4 is appliedacross the opposing faces of the plate. The direction of the electricfield is indicated by arrows 22. Thereafter, switches SI and S2 may bereturned to positions as shown in FIG. 2 for a subsequent readoutoperation.

Binary information may be stored in memory late 12 by applying anelectric field between the opposing faces of the plate in either one oftwo directions, so that the plate stores either a binary I or a binaryOsignal. Layer I6 is connected to a single pole switch S3. Switch S3serves to connect layer 16 with either a ground potential, or a 8+source of polarizing potential, or to an output-circuit OUT. When it isdesired to store a binary 1 signal in memory plate 12, switches S2 andS3 are manipulated so that B+ potential is applied to layer 16 andground potential is applied to layer 20. As shown in FIG. 2, however,plate I2 stores a binary signal, which results from having appliedB-lpotential to layer and ground potential to layer 16.

With switches S1, S2 and S3 in the positions as shown in FIG. 2, aninterrogating input voltage V is applied to layer 18. If the appliedvoltage V is of a polarity opposite to the direction of polarization ofthe drive plate, then the magnitude of this interrogation voltage iskept well below the polarization voltage threshold, i.e., the voltagerequired to permanently polarize drive plate I4, so that the readoutprocess is nondestructive. Application of the readout voltage pulsecauses the drive plate to contract or expand in the direction dependenton its prepolarization, as well as the polarity of the applied readoutvoltage pulse. The direction of contraction or expansion will be bothlaterally and perpendicularly of the plane defined by plate 14. Sinceplates I2 and 14 are bonded together, as by the layer 20 of conductiveepoxy, any change in physical dimensions of plate 14 will causecorresponding changes in physical dimensions of plate 12. When thememory plate is thus stressed, it develops a voltage which appearsbetween layers 16 and 20, with the polarity at layer 20 being positiveor negative, dependent on the state of prepolarization of the memoryplate, as well as the direction of mechanical stress. Thus, withreference to FIG. 2, the output voltage V,, will be a negative pulserepresentative that a binary 0 signal is stored by plate 12. For afurther description of a ceramic memory device as shown in FIG. 2,reference should be made to US Pat. application Ser. No. 640,717.

CERAMIC MEMORY MATRIX Having now described a single bit ceramic memorydevice, together with the manner in which binary information is storedand interrogated, reference is now made to the ceramic memory matrix ofFIG. 3. This matrix includes two word line memories TMl and TM2 which,for example, may correspond with the work line memories TMl and TM2 ofthe ceramic memory matrix TM of FIG. I. As shown in FIG. 3, each wordline memory TMl and TM2 includes four single bit ceramic memory devices10a, 10b, 10c and 10d, each corresponding with the single bit ceramicmemory device I0 illustrated in FIG. 2. The common lines of memorydevices 10a, 10b, I00, I 0d in word line memory TMl are connected towrite circuits W1, W2, W3 and W4, respectively. Similarly, the bit linesof ceramic memory devices 10a, 10b, 10c, 10d of word line memory TMI arealso connected to write circuits W1, W2, W3, W4. Also, in a similarmanner, the common lines and bit lines of ceramic memory devices 10a,I0b,.l0c, 10d of word line memory TM2 are connected to write circuitsW5, W6, W7, W8.

Each write circuit may be identical and take the form as write circuitWI, shown in detail in FIG. 3. The write circuit WI corresponds with thecircuitry shown in FIG. 2 and includes switch S2 and switch S3. SwitchS2 serves to selectively connect the common line of ceramic memorydevice 111a with either ground potential or B+ potential or opencircuit, and switch S3 serves to respectively connect the bit line ofmemory device 10a with either ground potential or B+ potential or opencircuit. The drive lines of ceramic memory devices 10a, Ifib, 10c, 10din word line memory TMI are connected together in common and, thence,through a normally open switch S4 to a C+ voltage supply source in asequence interrogator circuit I Similarly, the drive line conductors ofceramic memory devices 10a, 10b, 10c, 10d in word line memory TM2 areconnected together in common and thence through a switch S4 to a C+voltage supply source in an interrogator circuit 1,.

In operation, switches S2, S3 in each of the write circuits WI throughW8 may be manipulated to prepolarize the memory plate in word linememories TMI and TM2. This writing function is the same for each memorydevice as previously described with reference to FIG. 2. As shown by thedirection of the arrows on the memory plates I2 in word line memory TMl,the pattern of binary signals stored by the four memory devices is0-1-0-I. Similarly, as shown by the arrows on the memory plates I2 inword line memory TM2, the pattern of binary signals stored is 0-1-1-1.Thus, the decimal number of the weighted binary content of word linememory TMI is 5 and the decimal number of the weighted binary content ofword line memory TM2 is 7.

Upon closure of switch S4 in the interrogation circuit l the pattern ofthe binary signals on the bit lines taken from the four ceramic memorydevices of word line memory TMl will be 0-1-0-1. Similarly, when switchS4 in interrogator circuit I, is closed, the pattern of the binarysignals on the bit lines of the ceramic memory devices of word linememory TM2 will be 0-1-1-1. As previously discussed with reference toFIG. 2, the duration of the output voltage V, on each bit linecorresponds in time with the duration of the interrogating voltage V,,,.Accordingly, the pattern of open circuit binary signals obtained on thebit lines of word line memory TMI or word line memory TM2 exhibits atime duration in accordance with the time duration of application of theinterrogating voltage, i.e., the time duration that switch S4 ininterrogating circuit I is closed, or that switch S4 in interrogatingcircuit I is closed.

SEQUENCE CONTROLLER.

Having now described a ceramic memory matrix, circuitry for altering thebinary information stored, and circuitry for interrogating the matrix, adescription is now presented as to the manner in which the matrix isinterconnected with various circuits to provide a load sequencecontroller. As shown in FIG. 1, the load sequence controller includes analternating voltage source V which may take any suitable form, such as a60 cycles per second line frequency source. The pulse source circuit Sis coupled to voltage source V and includes a suitable frequencydividing circuit 30 which serves to divide the 60 cycles per secondfrequency of source V into a frequency of 1 cycle per second. The outputof frequency divider 30 is applied to a shaper 32 so as to provide atrain of equi-timespaced pulses exhibiting a frequency of one pulse persecond. Binary counter C is coupled to pulse source S to receive thetrain of equi-time-spaced pulses. This binary counter is a four stagecounter and has four outputs a, b, c, d which have decimal weights of 8,4, 2, 1, respectively, for providing apatternofbinarysignals,thedecirnalwdghtofwhichincreaseslnaecordanccwiththedecimalnumberofthepulscscountedflhe four outputs'a, b,c, d of the binary counter C are coupled to a binary comparator BC.

The ceramic memory matrix TM includes four word line memories TMl, TM2,TM3 TM4, each of which may be constructed as a schematically illustratedin FIG. 3 with respect to word line memories TMl and TM2. Preferably,however, this matrix is constructed in accordance with an improvedmatrix disclosed in our previously identified US. Pat. application, Ser.No. 640,7l7. As shown in FIG. 3, each of the four word line memoriesincludes four ferroelectric bistable memory means which serve to store abinary I or a binary O-signal so that the decimal number of the weightedbinary content of a word line memory is representative of a desired timeduration for an associated load interval. Each of these memory means a,10b, I 0c, [0d in FIG. 3, has an input in the form of a drive line whichare all connected together in common for any one word line memory andthence to one of the outputs l, 2, 3 or 4 of the interrogator I forreceiving interrogation signals. Also, each of these bistable memorymeans has an output in the form of a bit line which serves to carry abinary signal in response to receipt of an interrogation signal. Thesebit lines for associated bits in the various word line memories may beconnected together, as shown in FIG. 3. The bit line output circuits ofthe matrix TM include circuits g, h, i and j, which are respectivelycoupled through bit line amplifiers Al, A2, A3 and A4 to a type D, fourstage flip-flop register R1. Register R1 includes four D type flip-flopsFFI, FF2, FF3 and FF4, each having a set tenninal S and a toggleterminal T. The outputs of amplifiers Al through A4 are respectivelyconnected to set terminals S of flip flops FF 1 to FF4. The outputcircuits of these four flip-flops are connected to binary comtor BC. Ina manner similar to the outputs of binary counter C, the bit line outputcircuits g, h, i and j of matrix TM and the corresponding outputs ofregister R1 have decimal weights of 8, 4, 2 and l, respectively.

The output of the binary comparator BC is connected to a reset input ofthe binary counter C, a reset input of register R1, and to the input ofthe sequence-interrogator circuit l. Circuit l may'take the form of acirculating ring counter having its output circuits 1, 2, 3 and 4respectively connected to the commonly connected drive lines of wordline memories TMl, TM2, TM3 and TM4. The interrogator circuit I servesto sequentially energize its output circuits 1, 2, 3 and 4 in a cyclicalfashion in response to actuating trigger pulses received from the binarycomparator BC. The equivalent function of interrogator circuit I is thatas performed by interrogator circuits I, and I, shown in simplified formin FIG. 3. Diodes D1 to D4, poled as shown in FIG. I, connect the fouroutput circuits of interrogator circuit I in common and thence to thetoggle terminals T of the four stage flip-flop register R1.

Interval time write circuit-TW has four outputs respectively coupled toword line memories TM L TMZ, TM3 and TM4 for purposes of electricallyaltering the binary state of each memory means in the associated workline memories. This circuitry may take the form as shown by thesimplified circuit W1 in FIG. 3 or, alternatively, may take the form ofmore complex solid state, static element automatic writing circuitry.

The output circuits 1, 2, 3 and 4 of the sequence-interrogator circuit Iare coupled to a load control circuit LC. This load control circuitincludes signal amplifiers 34, 36, 38 and 40 which are respectivelyconnected to output circuits I, 2, 3 and 4 of circuit l. The output ofamplifier 34 is coupled to a main street go signal light MSG, as well asthrough a diode 42, poled as shown, to a cross street red signal lightCSR. The output of signal amplifier 36 is coupled through a diode 44,poled as shown, to signal light CSR and directly to a main street yellowsignal light MSY. The output of signal amplifier 38 is coupled to across street go signal light CSG as well as though a diode 46, poled asshown, to a main street red signal light MSR. The output of signalamplifier 40 is coupled to a cross street yellow signal light CSY aswell as through a diode 48, poled as shown, to signal light MSR.

OPERATION The four word line memories of memory matrix TM serve to storebinary'signals-representative of the desired time duration for thevarious traffic. intervals to be allocated and timed. In the example ofFIG. 1, only four traffic intervals are allocated and timed; to wit,main street go, main street yellow, cross street go, and cross streetyellow intervals. The time durations for these four intervals arerepresented by the binary signals stored in word line memories TMI, TM2,TM3 and TM4, respectively. The binary signals stored in these word linememories should be written as desired. Thus, for example, both cautionintervals may have a time duration of 3 seconds each. If so, then thecircuitry in the interval time write circuit TW is manipulated so thatthe pattern of binary signals stored in word line memories TM2 and TM4is 0-0-1-1 which, as is well known, has a decimal weight equal to thedecimal number 3. This pattern of binary signals is indicated on wordline memories TM2 and TM4 in FIG. 1. Similarly, it may be desired thatthe time duration for the main street go interval be 9 seconds.Accordingly, the time write circuit TW is manipulated sothat the memorymeans in word line memory TMI stores a binary signal pattern 1-0-0-l,which is equal to the decimal number 9. This is shown on word linememory TMI in FIG. 1. Lastly, the cross street go interval may be setfor 8 seconds which, as shown on memory word line TM3 in FIG. 1, is thebinary signal pattern 1-04-0. It is to be appreciated, however, that theassumed durations of these various intervals is for purposes ofillustration only, and in practice the time durations are normallylonger than that presented in this example.

With matrix TM having its memories written as discussed above, theoperation commencing with the main street go interval will now bepresented. The main street go interval commences when thesequence-interrogator circuit I energizes its output circuit 1 inresponse to receipt of a trigger pulse from binary comparator BC. Theoutput signal carried by circuit 1 is a positive signal, as representedby voltage V in FIG. 2, and serves to interrogate word line memory TMl.This interrogating signal has a duration which until the interrogationcircuit I receives another trigger pulse from binary comparator BC.During this time period, each of the memory means in word line memoryTMl is interrogated to provide a pattern of binary signals on outputcircuits 3, h, i and j. This pattern of binary signals is in accordancewith the state of prepolarization of each memory plate 12 in the severalmemory means being interrogated. The interrogation signal also permitsregister R1 to receive this pattern of binary signals from circuits g,h, i and j and provide the same pattern of signals at its outputcircuits for the duration of the interrogation signal. This pattern ofbinary signals is applied to the binary comparator BC.

At the same time that the sequence-interrogator circuit I was actuatedby a trigger pulse to energize its output'circuit l, the register R1 wasreset, or cleared, and the binary counter C was reset to again countpulses from sourceS and provide a pattern of binary signals on itsoutput circuits a, b, c, and d, which pattern changes in accordance withthe decimal number of the pulses counted. Initially then, the pattern ofoutput signals on circuits a, b, c and d is -0-0-0. After the firstpulse has been counted, the pattern changes to 0-0-0-1 and, then, uponthe second pulse the pattern changes to 0-0-1 -0. When nine pulses havebeen counted the pattern of binary signals on outputs a, b, c and dbecomes 1-0-0-1. At that point in time the pattern of binary signalsreceived from the binary counter C is the same as that received fromregister RI and a match is obtained. Each time such a match is obtained,the binary comparator BC provides an output trigger pulse which isapplied to the sequence-interrogator circuit l to energize the nextoutput circuit, in this case output circuit 2, as well as to reset thebinary counter C to a zero reading and to reset, or clear, register R1.During the time duration that the nine pulses were being counted bybinary counter C, output circuit 1 of the sequence-interrogator circuitI was energized to, in turn, energize both the main street go signallight MSG and the cross street red signal light CSR.

- 'When the main street green interval has timed out, i.e., when thebinary comparator BC provides an output trigger signal, thesequence-interrogator is actuated so as to deenergize its output circuit1 and energize its output circuit 2. At the sanre time, binary counter Cis reset to a zero reading and register R1 is reset..'lhe cross streetyellow interval is now allocated since a circuit is completed throughsignal amplifier 36 to energize the main street yellow signal lamp MSY,as well as the cross street red signal lamp CSR. The energization ofoutput circuit 2 of interrogator circuit I serves to interrogate thememory means in the word line memory TM so that the output circuits 3,Ir, i and j of matrix TM now carry the binary signal pattern 0-0-14.This pattern of signals is now carried by the four output circuits ofregister RI and applied to binary comparator BC. When three pulses frompulse source 8 have been counted, the pattern of binary signals onoutput circuits 0, b, c and d of binary counter C is 0-0-l-l and a matchis ob- Thus, binary comparator BC provides a second trigger signal toreset binary counter C, to reset register R1 and to acmate thesequence-interrogator circuit I. This operation continues for each ofthe intervals in the same manner as described above, and in a cyclicalfashion. The cross street red and main street red signal displays arenot in themselves allocated and since, as is conventional, signal lightsMSR and CSR are energized whenever the conflicting phase go and yellowlights are energized. In the event it is desired to change the timeduration for one of the timed intervals, the interval time write circuitTW is employed as in the manner discussed previously with respect toFIG. 3, so as to change the binary signals stored by the word linememory associated with the interval to be changed.

SECOND EMBODIMENT Referring now to FIG. 4, there is shown a secondembodiment of the invention. This embodiment is quite similar to that vas shown in FIG. I, and, accordingly, like components in both FIGS. are.identified with like character references. Before discussing theadditional circuitry, a few comments are in order with respect tomodifications made in' circuitry found in FIG. 4, which compares withcorresponding circuitry in FIG. 1. Thus, binary counter C in FIG. 4 isshown as a six stage binary counter, having s'ix outputs a, b, c, d, eand f, having decimal weights of 32, I6, 8, 4, 2, I. The interval timestorage ceramic memory matrix TM of FIG. 4 now includes six word linememories TMl through TM6. Also, each word line memory includes six bitsinstead of the four bits shown in FIG. 1. Accordingly, the memory matrixTM has six bit line output circuits g, h, i, j, k and 1, having decimalweights of 32, I6, 8, 4, 2, I. Register R1 is a six stage flip-flopregister coupled to the output circuits g through by meansiof amplifiersAl to A6. The interval time write circuit W has additional ci r-.

cuitry so that it has the capacity of altering the binary signals storedby six word line memories, as opposed to the four word line memories ofFIG. 1. Likewise, the sequence-interrogator I has six outputs, i.e., itis a six stage circulating ring counter,

coupled to the six commonly connected drive lines of the six word linememories TM] through TM6.

In the embodiment of FIG. 4, an interval program storage ceramic memorymatrix PM is interposed between the output circuits of thesequence-interrogator circuit I and the load control circuit LC. Memorymatrix PM is a 3 bit, six word line desired by an interval program writecircuit PW which may be constructed in the same manner as is writecircuit W. The drive lines for matrix PM are connected to outputcircuits 1 through 6 of interrogator circuit 1. Matrix PM has three bitline output circuits p, g, r respectively having decimal weights 7 'of4, 2 and l. The three bit line output circuits p, 3, ref memory matrixPM are respectively coupled through amplifiers A7,'A8 and A9 to a threestage, type D, flip-flop register R2. Register R2has three flip-flopsFF7, FF8 andFF9, each corresponding with flip-flop in register R1 or R1.The three outputs of register R2 are coupled to a decimal decoder BD,such as a diode matrix, having six output circuits s, t, u, v,

w and x.

The load control circuit LC is quite similar to that of load controlcircuit LC. The inputs of signal amplifiers 34, 36, 38 and 40 'arerespectively taken at outputs t, u, w and x ofthe binary to decimaldecoder BD. In addition to the circuitry shown in FIG. 1, load controlcircuit LC also-includes a signal amplifier 50 having its inputconnected to output circuit s'of decoder BD and its output connected toa main street green advance signal light MSGI. An additional diode'52,poled as shown in FIG. 4', connects the output of amplifier 50 with thecross street red signal light CSR. The load control circuit DC alsoincludes a signal amplifie 54 having its inputconnected to the outputcircuit v of the decoder BD, and its output connected to a cross streetad-..

vance green light CSGl..Another diode 56, poled as shown, connects theoutput or signal amplifier 54 with the main street red signal light MSR.The main street advance light MSGl and the cross street advance signallight CSGl may, for

example, take the form of left turn arrows,'which are In-- and decoderED, is essentially the same as that discussed hereinbefore with respectto the embodiment of FIG. 1. Thus, sequencer l' serves to sequentiallyapply interrogating signals to the interval time storage wordlinememories TMI through TM6. Each time that the pattern of binary signalson the output circuits of registerRl is the same as the pattern ofbinary signals on output circuits 0 through f of counter C, the binarycomparator BC resets the binary counter C', resets register RI, andactuates the interrogator I to apply an interrogating signal to the nextsucceeding word line memory. In this em bodirnent, however, outputcircuits 1 through 6 of the sequence-interrogator circuit I arerespectively coupled to of the pattern of binary signals on the bit lineoutput circuits p through r. That is, circuit s is energized wheneverthe decimal weight is l (binary code 001), circuit 1 is energized whendecimal weight is 2 (binary code 010), circuit u is energized when thedecimal weight is 3 (binary code 011), circuit v is energized when thedecimal weight is 4 (binary code 100), circuit w is energized when thedecimal weight is 5 (binary code 101), and circuit x is energized whenthe decimal weight is 6 (binary code 110).

If it is desired that all of the timed intervals be'allocated and thatthey be allocated in a predetennined order of: main street advancegreeri; main street green; main street yellow; cross street advancegreen; cross street green; and, cross street yellow, then the intervalprogram storage memory matrix PM should be written to reflect thispredetermined order. Accordingly, the write circuit TW is actuated sothat word line memories PMl through PM6 respectively store binarysignals having decimal weights of l, 2, 3, 4, 5 and 6. The pattern ofbinary signals for this order is indicated on word line memories PM1through PM6 in FIG. 4.

With the matrix PM being written in the predetennined order discussedabove, it will be appreciated when word line memory PM! is interrogatedsimultaneously with the interrogation of word line memory TMl, thepattern of binary signals on the output circuits p through r of matrixPM is 001. With this pattern of binary signals applied to decoder BD thedecoder's output circuit s is energized so as to energize main streetgreen advance signal light MSGl as well as the cross street red sigtallight CSR. When the binary comparator BC again actuates thesequence-interrogator l, word line memories TMZ and PM2 areinterrogated. Thus, only output circuit t of decoder ED is energized,whereupon main street green advance signal light MSG! is deenergized andmain street green signal light MSG is energized. This sequence ofoperation is continued through the remaining word line memories and thenthe sequence is repeated in a cyclical fashion.

It may be desired to change the interval program, as by eliminating themain street green advance interval and allocating the time previouslygiven to that interval to the main street green interval. In such casethe write circuit TW is actuated so as to rewriteword line PMl so thatit stores the sanne pattern as binary signals being stored by word linememory PM2, i.e., 010. In this case, when output circuit 1 of thesequence-interrogator l is energized, word line memories PMl and TMl areinterrogated. However, since the binary content of word line memory PM1has been changed, the bit line output circuits p through r now carry thebinary signal pattern 0-1-0. Accordingly, only output circuit 1 ofdecoder BD is energized so as to energize both the main street greensignal light MSG and the cross street red signal light CSR. 'llne mainstreet green advance signal light MSGl was not energized. Afterinterrogator l is again actuated, word line memory PM2 is interrogatedand the bit line output lines p through r carry the same binary sigrnalpattern; to wit, 0-1-0, and again only output circuit r of decoder 80 isenergized.

1n the event it is desired to completely eliminate the main street greeninterval, word line memory PM is altered so that the pattern of binarysignals is 0-0-0, and, in addition, word line memory TM is altered-sothat its pattern of binary stored signals is 0-0-0. In this event, oncethe sequence-interrogator circuit 1' is actuated to energize its outputcircuit 1, the pattern of binary sigials applied to bit line outputcircuits g through I has a decimal weight of zero. Since the binarycounter has been reset to zero, a match is obtained and the binarycomparator BC' actuates the sequence-interrogator l to energize itsoutput circuit 2. Also, during this momentary period that output circuit1 is energized, the pattern of binary signals on bit lines p through rof matrix PM is of a decimal weight of zero and, accordingly, none ofthe decoder output circuits .9 through x are energized.

Another function that may be performed by the embodiment shown in FIG.4, is that one of the intervals may be timed without a correspondingload being energized. This function,

while perhaps not of significance to the art of traffic control, hasapplications in process control fields where it is desired to have atimed off condition. This function may be performed, forexample, byrewriting one of the program word line memories to store a zero signal.Thus, for example, program word line memory PMS may be rewritten tostore the binary signal pattern 0-0-0. Accordingly, when word linememory TM3 is,

interrogated, a certain period of time will elapse, in accordance withthe binary signals stored in memory TM3, until the sequence-interrogatorcircuit l' is actuated to interrogate word line memory TM4. During thisperiod, however, the output circuits of register R2 carry a binarysignal pattern of 0-0- -0. Thus, no load will be energized.

Although the invention has been shown in connection with preferredembodiments, it will be readily apparent to those skilled in the an thatvarious changes in form and arrangement of parts may be made to suitrequirements without departing from the spirit and scope of theinvention as defined by the appended claims.

We claim:

1. Apparatus for sequentially allocating and timing a plurality of loadintervals and comprising:

a plurality of interval time storage memories each corresponding with anassociated load interval to be timed, each said memory including:plurality of electrically alterable and electrically interrogatablebistable memory means each storing a binary one of a binary zero signalso that the weighted binary content of a said memory is a decimal numberrepresentative of a desired time duration for an associated loadinterval, each said memory means having an input for receiving aninterrogation signal and an output for carrying a said binary signal inresponse to receipt of an interrogation signal;

interrogating means for sequentially applying interrogation signals tosaid plurality of memories so that when any one memory is interrogatedthe outputs of its plurality of memory means provide a pattern of saidbinary signals; a source of equi-time spaced pulses; and, means foractuating said interrogating means to interrogate the next succeeding ofsaid plurality of memories when the decimal number of the said pulsesreceived is equal to the decimal weight of the pattern of binary signalson the outputs of the memory means of the memory last interrogated,

each bistable memory means comprising an easily polarized ferroelectricmemory plate, a drive plate having the property of changing itsdimensions upon application of an electrical signal and beingpemnanently polarized, said plates being mounted with facing surfaceshaving an interposed conductive layer, an output conductive layer on theremaining surface of the memory plate and an input conductive layer onthe remaining surface of the drive plate, the input and output of thememory means being connected to the said input and output conductivelayers respectively.

2. Apparatus as set forth in claim 1 wherein said interrogating meansincludes a plurality of outputs, corresponding in number with saidplurality of memories, for sequentially carrying said interrogationsignals.

3. Apparatus as set forth in claim 2 wherein said interrogation meansincludes circuit means responsive to each actuation by said actuatingmeans to sequentially energize said interrogating outputs one at a timeto carry a said interrogation signal for a time duration extending untilsaid interrogation means is again actuated by said actuating means.

4. Apparatus as set forth in claim 3 including load interval controlmeans coupled to each said interrogating output to control allocation ofsaid load interval for a time duration in accordance with the timeduration a said interrogation signal is carried by the saidinterrogating output.

5. Apparatus as set forth in claim 1 including interval time writingcircuit means for electrically altering said memory means to selectivelychange the binary states of the stored binary signals.

6. Apparatus as Set forth in claim 1 wherein each said bistable memorymeans includes ferroelectric storage capacitor memory plate means havinga surface, said plate means adapted to be polarized in one of two stablestates; and, piezoelectric driving plate means having a portion thereofsecured to at least a portion of said surface in such a manner thatapplication of a said interrogation signal to said driving plate meanscauses transmission of mechani-- cal forces to said memory plate meansin directions acting both laterally and perpendicularly of said surfaceso that said memory plate means provides an output voltage signal of apolarity in accordance with the state of polarization of said memoryplate means.

7. Apparatus for sequentially allocating and timing a plurality of loadintervals and comprising:

a plurality of interval time storage memories each corresponding with anassociated load interval to be timed;

a plurality of interval program storage memories each corresponding withan associated load interval to be allocated;

each of said memories including:

a plurality of electrically alterable and electrically interrogatablebistable memory means each storing a binary one or a binary zero signalso that the weighted binary content of a said memory is a decimalnumber, each said memory means having an input for receiving'aninterrogation signal and an output for carrying a said binary signal inresponse to receipt of an interrogation signal; I

interrogation means for sequentially applying interrogation signalssimultaneously to different pairs of memories from said two pluralitiesof memories, whereby the outputs of each memory of said pair ofsimultaneouslyinterrogated memories carry a pattern of said binarysignals;

a source of equi-time-spaced pulses; and,

means for actuating said interrogating means to interrogate the nextsucceeding pair of memories when the decimal number of the said pulsesreceived is equal to the decimal weight of the pattern of binary signalson the outputs of the memory means of the interval time storage memorylast interrogated.

8. Apparatus as set forth in claim 7 wherein said plurality of intervaltime storage memories correspond in number with said plurality ofinterval program storage memories, and said interrogating means includesa plurality of outputs, corresponding in number with each said pluralityof memories, for sequentially carrying said interrogation signals.

9. Apparatus as set forth in claim 8 wherein said interrogation meansincludes circuit means responsive to each actuation by said actuatingmeans to sequentially energize said interrogation outputs one at a timeto carry a said interrogation signal for a time duration extending untilsaid interrogation means is again actuated by said actuating means.

10. Apparatus as set forth in claim 9 including binary signal decodingmeans coupled to the outputs of each said memory of said plurality ofinterval program storage memories to provide a decimal outputrepresentative of which one of said interval program memories is beinginterrogated, and load interval control means coupled to said decodingmeans to control allocation of a particular load interval in accordancewith which one of said interval program memories is being interrogatedand for a corresponding time duration thereof.

11. Apparatus as set forth in claim 10 including interval programwriting circuit means for electrically altering said memory means ofsaid interval program storage memories to selectively change the binarystates of the binary signals stored therein.

12. Apparatus as set forth in claim 11 including interval time writingcircuit means for electrically altering said memory means of saidinterval time storage memories to selectively change the binary statesof the binary signals stored 4 therein.

13. Apparatus as set forth in claim 7 wherein each said bistable memorymeans includes:

ferroelectric storage capacitor memory plate means having a surface,said plate means adapted to be polarized in one of two stable states;and,

piezoelectric driving plate means having a portion thereof secured to atleast a portion of said surface in such a manner that application of asaid interrogation signal to said driving plate means causestransmission of mechanical forces to said memory plate means indirections acting both laterally and perpendicularly of said surface sothat said memory plate means provides an output voltage signal of apolarity in accordance with the state of polarization of said memoryplate means.

14. A traffic controller for sequentially allocating and timing aplurality of traffic intervals to be displayed by traffic signal lightmeans and wherein said traffic controller comprises:

a plurality of traffic interval time storage memories one each for eachsaid traffic interval to be allocated and timed, each said trafficinterval time storage memory including: I

a plurality of electrically alterable and electrically interrogatablebistable memory means each storing a binary. one or a binary zero signalso that the decimal number of the weighted binary content of a saidmemory is representative of a desired time duration for an associatedtrafi'rc interval, each said memory means having an input for receivingan interrogation signal and an output for carrying a said binary signalin response to receipt of an interrogation signal;

interrogating means for sequentially applying interrogation signals tosaid plurality of memories so that when any one memory is interrogatedthe outputs of its plurality of memory means provide a pattern of saidbinary signals;

a source of equi-time spaced pulses; and

means for actuating said interrogating means to interrogate the nextsucceeding of said plurality of memories when the decimal number of saidpulses received is equal to the decimal weight of the pattern of binarysignals on the outputs of the memory means of the memory lastinterrogated;

each bistable memory means being of the nondestructive readout, dualplate type comprised of an easily polarized memory plate and apermanently polarized drive plate, the plates having facing surfaceswhich are secured to each other.

15. A traffic controller as set forth in claim 14 wherein saidinterrogating means includes a plurality of outputs, corresponding innumber with said plurality of memories, for sequentially carrying saidinterrogation signals.

16. A traffic controller as set forth in claim 15 wherein saidinterrogation means includes circuit means responsive to each actuationby said actuating means to sequentially energize said interrogatingoutputs one at a time to carry a said interrogation signal for a timeduration extending until said interrogation means is again actuated bysaid actuating means.

17. A trafi'rc controller as set forth in claim 16 including trafficinterval control means coupled to each said interrogating output tocontrol allocation of a said trafiic interval for a time duration inaccordance with the tim duration a said interrogation signal is carriedby the said interrogating output.

18. A traffic controller as set forth in claim 14 wherein each saidbistable memory means includes:

ferroelectric storage capacitor memory plate means having a surface,said plate means adapted to be polarized in one of two stable states;and

piezoelectric driving plate means having a portion thereof secured to atleast a portion of said surface in such a manner that application ofsaid interrogation sigtal to said driving plate means causestransmission of mechanical forces to said memory plate means indirections acting both laterally and perpendicularly of said surface sothat said memory plate means provides an output voltage signal of apolarity in accordance with the state of polarization of said memoryplate means.

19. A traffic controller for sequentially allocating and timing aplurality of trafiic intervals to be displayed by trafiic signal lightmeans to' at least one direction of traffic flow and wherein saidtralfic controller comprises:

a plurality of traffic interval time storage memories each correspondingwith an associated traffic interval to be timed;

a plurality of trafiic interval program storage memories eachcorresponding with an associated traffic interval to be allocated;

each of said memories including:

a plurality of electrically alterable and electrically interrogatablebistable memory means each storing a binary one or a binary zero signalso that the weighted binary content of a said memory is a decimalnumber, each said memory means having an input for receiving aninterrogation signal and an output for carrying a said binary signal inresponse to receipt of an interrogation signal;

interrogating means for sequentially applying interrogation signalssimultaneously to different pairs of memories from said two pluralitiesof memories, whereby the outputs of each memory of said pair ofsimultaneously interrogated memories carry a pattern of said binarysignals;

a source of equi-time-spaced pulses; and

means for actuating said interrogating means to interrogate the nextsucceeding pair of memories when the decimal number of the said pulsesreceived is equal to the decimal weight of the pattern of binary signalson the outputs of the memory means of the interval time storage memorylast interrogated.

20. A traffic controller as set forth in claim 19 wherein each saidbistable memory means includes:

ferroelectric storage capacitor memory plate means having a surface,said plate means adapted to be polarized in one of two stable states;and

piezoelectric driving plate means having a portion thereof secured to atleast a portion of said surface in such a manner that application ofsaid interrogation signal to said driving plate means causestransmission of mechanical forces to said memory plate means indirections acting both laterally and perpendicularly of said surface sothat said plate means provides an output voltage signal of a polarity inaccordance with the state of polarization of said memory plate means.

21. A traffic controller as set forth in claim 19 wherein said pluralityof traflic interval time storage memories correspond in number with saidplurality of traffic interval program storage memories, and saidinten'ogating means includes a plurality of outputs, corresponding innumber with each said plurality of memories, for sequentially carryingsaid interrogation signals. I

22. A traffic controller as set forth in claim 21 wherein saidinterrogation means includes circuit means responsive to each actuationby said actuating means to sequentially energize said interrogatingoutputs one at a time to carry a said interrogation signal for atimeduration extending until saidinterrogationmeansisagainactuatedbysaidactuatingmeans.

23. A traflic controller as set forth in claim 22 including binarysignal decoding means coupled to the outputs of each said memory of saidplurality of interval program storage memories to provide a decimaloutput representative of which one of said interval program memories isbeing interrogated, and traffic interval control means coupled to saiddecoding meats to control allocation of a particular traffic interval inaccordance with which one of said traffic interval program memories isbeing interrogated and for a corresponding time duration thereof.

24. A traffic controller as set forth in claim 23 including tralficprogram writing circuit means for electrically altering said memorymeans of said traffic interval program storage memories to selectivelychange the binary states of the binary signals stored therein.

25. A traffic controller as as set forth in claim 24 including trafficinterval time writing circuit means for electrically altering saidmemory means of said traffic .interval time storage memories toselectively change the binary states of the binary signals storedtherein.

26. Apparatus for selectively programming a plurality of loads andcomprising:

a plurality of electrically alterable and electrically interrogatablebistable memory means each storing a binary one or a binary zero signal,each said memory means having an input circuit means for receiving aninterrogation signal and an output circuit means for carrying a saidhinary signal in response to the receipt of an interrogation s ginterrogation means for applying interrogation signals to saidpluralityof memory means so that when a said memory means is interrogated theoutput circuit means of said memory means carries a binary signalrepresentative of the binary signal stored in said bistable memorymeans, said interrogating means having an input circuit means forreceiving input-pulse signals and a plurality of output circuit means,one coupled to each said memory means, I

for respectively carrying a said interrogation signal in accordance withthe number of received input pulse signals; and circuit means connectedto said output circuit means of said plurality of memory means andadapted to be connected to a load;

each bistable memory means being of the nondestructive readout, dualplate type comprising an easily polarized memory plate and a pennanentlypolarized drive plate, the plates having facing surfaces which aresecured to each other.

27. Apparatus as set forth in claim 26 wherein said interrogating meansincludes circuit means for sequentially energizing its output circuitmeans in accordance with the number of received input pulse signals tothereby sequentially apply interrogating signals to said plurality ofmemory means.

28. Apparatus as set forth in claim 27 including a source of time spacedpulses; and,

said interrogation means being coupled to said pulse source forinterrogating the next succeeding of said plurality of memory means inthe response to the receipt of said pulse.

29. Apparatus as set forth in claim 26 wherein each said bistable memorymeans includes:

ferroelectric storage capacitor memory plate means having a surface,said plate means adapted to be polarized in one of two stable states;and,

piezoelectric driving plate means having a portion thereof secured to atleast a portion of said surface in such a manner that application of asaid interrogation signal to said driving plate means causestransmission of mechanical forces to said memory plate means indirections acting both laterally and perpendicularly of said surface sothat said memory plate means provides an output voltage signal of apolarity in accordance with the state of polarization of said memoryplate means.

30. Apparatus as set forth in claim 26 wherein said plurality ofbistable memory means is a ferroelectric capacitor matrix and includes aplurality of rows each including at least one ferroelectric storagecapacitor memory means; and,

each of said plurality of output circuit means of said interrogatingmeans respectively carry a said interrogation signal to therebyinterrogate a selected row of said ferroelectric storage memory means.

31. Apparatus as set forth in claim 30 wherein each said row offerroelectric storage capacitors includes a plurality of ferroelectricstorage memory means each corresponding with an associated load; and,

rogated the output circuit means of said plurality of memory means carrya pattern of binary signals representative of the binary states of saidinterrogated row of ferroelectric memory means.

1. Apparatus for sequentially allocating and timing a plurality of loadintervals and comprising: a plurality of interval time storage memorieseach corresponding with an associated load interval to be timed, eachsaid memory including: a plurality of electrically alterable andelectrically interrogatable bistable memory means each storing a binaryone of a binary zero signal so that the weighted binary content of asaid memory is a decimal number representative of a desired timeduration for an associated load interval, each said memory means havingan input for receiving an interrogation signal and an output forcarrying a said binary signal in response to receipt of an interrogationsignal; interrogating means for sequentially applying interrogationsignals to said plurality of memories so that when any one memory isinterrogated the outputs of its plurality of memory means provide apattern of said binary signals; a source of equi-time spaced pulses;and, means for actuating said interrogating means to interrogate thenext succeeding of said plurality of memories when the decimal number ofthe said pulses received is equal to the decimal weight of the patternof binary signals on the outputs of the memory means of the memory lastinterrogated, each bistable memory means comprising an easily polarizedferroelectric memory plate, a drive plate having the property ofchanging its dimensions upon application of an electrical signal andbeing permanentlY polarized, said plates being mounted with facingsurfaces having an interposed conductive layer, an output conductivelayer on the remaining surface of the memory plate and an inputconductive layer on the remaining surface of the drive plate, the inputand output of the memory means being connected to the said input andoutput conductive layers respectively.
 2. Apparatus as set forth inclaim 1 wherein said interrogating means includes a plurality ofoutputs, corresponding in number with said plurality of memories, forsequentially carrying said interrogation signals.
 3. Apparatus as setforth in claim 2 wherein said interrogation means includes circuit meansresponsive to each actuation by said actuating means to sequentiallyenergize said interrogating outputs one at a time to carry a saidinterrogation signal for a time duration extending until saidinterrogation means is again actuated by said actuating means. 4.Apparatus as set forth in claim 3 including load interval control meanscoupled to each said interrogating output to control allocation of saidload interval for a time duration in accordance with the time duration asaid interrogation signal is carried by the said interrogating output.5. Apparatus as set forth in claim 1 including interval time writingcircuit means for electrically altering said memory means to selectivelychange the binary states of the stored binary signals.
 6. Apparatus asset forth in claim 1 wherein each said bistable memory means includes:ferroelectric storage capacitor memory plate means having a surface,said plate means adapted to be polarized in one of two stable states;and, piezoelectric driving plate means having a portion thereof securedto at least a portion of said surface in such a manner that applicationof a said interrogation signal to said driving plate means causestransmission of mechanical forces to said memory plate means indirections acting both laterally and perpendicularly of said surface sothat said memory plate means provides an output voltage signal of apolarity in accordance with the state of polarization of said memoryplate means.
 7. Apparatus for sequentially allocating and timing aplurality of load intervals and comprising: a plurality of interval timestorage memories each corresponding with an associated load interval tobe timed; a plurality of interval program storage memories eachcorresponding with an associated load interval to be allocated; each ofsaid memories including: a plurality of electrically alterable andelectrically interrogatable bistable memory means each storing a binaryone or a binary zero signal so that the weighted binary content of asaid memory is a decimal number, each said memory means having an inputfor receiving an interrogation signal and an output for carrying a saidbinary signal in response to receipt of an interrogation signal;interrogation means for sequentially applying interrogation signalssimultaneously to different pairs of memories from said two pluralitiesof memories, whereby the outputs of each memory of said pair ofsimultaneously interrogated memories carry a pattern of said binarysignals; a source of equi-time-spaced pulses; and, means for actuatingsaid interrogating means to interrogate the next succeeding pair ofmemories when the decimal number of the said pulses received is equal tothe decimal weight of the pattern of binary signals on the outputs ofthe memory means of the interval time storage memory last interrogated.8. Apparatus as set forth in claim 7 wherein said plurality of intervaltime storage memories correspond in number with said plurality ofinterval program storage memories, and said interrogating means includesa plurality of outputs, corresponding in number with each said pluralityof memories, for sequentially carrying said interrogation signals. 9.Apparatus as set forth in claim 8 wherein said interrogation meansincludes circuit means responsive to each actuation by said actuatingmeans to sequentially energize said interrogation outputs one at a timeto carry a said interrogation signal for a time duration extending untilsaid interrogation means is again actuated by said actuating means. 10.Apparatus as set forth in claim 9 including binary signal decoding meanscoupled to the outputs of each said memory of said plurality of intervalprogram storage memories to provide a decimal output representative ofwhich one of said interval program memories is being interrogated, andload interval control means coupled to said decoding means to controlallocation of a particular load interval in accordance with which one ofsaid interval program memories is being interrogated and for acorresponding time duration thereof.
 11. Apparatus as set forth in claim10 including interval program writing circuit means for electricallyaltering said memory means of said interval program storage memories toselectively change the binary states of the binary signals storedtherein.
 12. Apparatus as set forth in claim 11 including interval timewriting circuit means for electrically altering said memory means ofsaid interval time storage memories to selectively change the binarystates of the binary signals stored therein.
 13. Apparatus as set forthin claim 7 wherein each said bistable memory means includes:ferroelectric storage capacitor memory plate means having a surface,said plate means adapted to be polarized in one of two stable states;and, piezoelectric driving plate means having a portion thereof securedto at least a portion of said surface in such a manner that applicationof a said interrogation signal to said driving plate means causestransmission of mechanical forces to said memory plate means indirections acting both laterally and perpendicularly of said surface sothat said memory plate means provides an output voltage signal of apolarity in accordance with the state of polarization of said memoryplate means.
 14. A traffic controller for sequentially allocating andtiming a plurality of traffic intervals to be displayed by trafficsignal light means and wherein said traffic controller comprises: aplurality of traffic interval time storage memories one each for eachsaid traffic interval to be allocated and timed, each said trafficinterval time storage memory including: a plurality of electricallyalterable and electrically interrogatable bistable memory means eachstoring a binary one or a binary zero signal so that the decimal numberof the weighted binary content of a said memory is representative of adesired time duration for an associated traffic interval, each saidmemory means having an input for receiving an interrogation signal andan output for carrying a said binary signal in response to receipt of aninterrogation signal; interrogating means for sequentially applyinginterrogation signals to said plurality of memories so that when any onememory is interrogated the outputs of its plurality of memory meansprovide a pattern of said binary signals; a source of equi-time spacedpulses; and means for actuating said interrogating means to interrogatethe next succeeding of said plurality of memories when the decimalnumber of said pulses received is equal to the decimal weight of thepattern of binary signals on the outputs of the memory means of thememory last interrogated; each bistable memory means being of thenondestructive readout, dual plate type comprised of an easily polarizedmemory plate and a permanently polarized drive plate, the plates havingfacing surfaces which are secured to each other.
 15. A trafficcontroller as set forth in claim 14 wherein said interrogating meansincludes a plurality of outputs, corresponding in number with saidplurality of memories, for sequentially carrying said interrogationsignals.
 16. A traffic controller as set forth in claim 15 wherein saidinterrogation means includes circuit means responsive tO each actuationby said actuating means to sequentially energize said interrogatingoutputs one at a time to carry a said interrogation signal for a timeduration extending until said interrogation means is again actuated bysaid actuating means.
 17. A traffic controller as set forth in claim 16including traffic interval control means coupled to each saidinterrogating output to control allocation of a said traffic intervalfor a time duration in accordance with the time duration a saidinterrogation signal is carried by the said interrogating output.
 18. Atraffic controller as set forth in claim 14 wherein each said bistablememory means includes: ferroelectric storage capacitor memory platemeans having a surface, said plate means adapted to be polarized in oneof two stable states; and piezoelectric driving plate means having aportion thereof secured to at least a portion of said surface in such amanner that application of said interrogation signal to said drivingplate means causes transmission of mechanical forces to said memoryplate means in directions acting both laterally and perpendicularly ofsaid surface so that said memory plate means provides an output voltagesignal of a polarity in accordance with the state of polarization ofsaid memory plate means.
 19. A traffic controller for sequentiallyallocating and timing a plurality of traffic intervals to be displayedby traffic signal light means to at least one direction of traffic flowand wherein said traffic controller comprises: a plurality of trafficinterval time storage memories each corresponding with an associatedtraffic interval to be timed; a plurality of traffic interval programstorage memories each corresponding with an associated traffic intervalto be allocated; each of said memories including: a plurality ofelectrically alterable and electrically interrogatable bistable memorymeans each storing a binary one or a binary zero signal so that theweighted binary content of a said memory is a decimal number, each saidmemory means having an input for receiving an interrogation signal andan output for carrying a said binary signal in response to receipt of aninterrogation signal; interrogating means for sequentially applyinginterrogation signals simultaneously to different pairs of memories fromsaid two pluralities of memories, whereby the outputs of each memory ofsaid pair of simultaneously interrogated memories carry a pattern ofsaid binary signals; a source of equi-time-spaced pulses; and means foractuating said interrogating means to interrogate the next succeedingpair of memories when the decimal number of the said pulses received isequal to the decimal weight of the pattern of binary signals on theoutputs of the memory means of the interval time storage memory lastinterrogated.
 20. A traffic controller as set forth in claim 19 whereineach said bistable memory means includes: ferroelectric storagecapacitor memory plate means having a surface, said plate means adaptedto be polarized in one of two stable states; and piezoelectric drivingplate means having a portion thereof secured to at least a portion ofsaid surface in such a manner that application of said interrogationsignal to said driving plate means causes transmission of mechanicalforces to said memory plate means in directions acting both laterallyand perpendicularly of said surface so that said memory plate meansprovides an output voltage signal of a polarity in accordance with thestate of polarization of said memory plate means.
 21. A trafficcontroller as set forth in claim 19 wherein said plurality of trafficinterval time storage memories correspond in number with said pluralityof traffic interval program storage memories, and said interrogatingmeans includes a plurality of outputs, corresponding in number with eachsaid plurality of memories, for sequentially carrying said interrogationsignals.
 22. A traffic controller as set forth in claim 21 wherein saidinterrogation means includes circuit means responsive to each actuationby said actuating means to sequentially energize said interrogatingoutputs one at a time to carry a said interrogation signal for a timeduration extending until said interrogation means is again actuated bysaid actuating means.
 23. A traffic controller as set forth in claim 22including binary signal decoding means coupled to the outputs of eachsaid memory of said plurality of interval program storage memories toprovide a decimal output representative of which one of said intervalprogram memories is being interrogated, and traffic interval controlmeans coupled to said decoding means to control allocation of aparticular traffic interval in accordance with which one of said trafficinterval program memories is being interrogated and for a correspondingtime duration thereof.
 24. A traffic controller as set forth in claim 23including traffic program writing circuit means for electricallyaltering said memory means of said traffic interval program storagememories to selectively change the binary states of the binary signalsstored therein.
 25. A traffic controller as as set forth in claim 24including traffic interval time writing circuit means for electricallyaltering said memory means of said traffic interval time storagememories to selectively change the binary states of the binary signalsstored therein.
 26. Apparatus for selectively programming a plurality ofloads and comprising: a plurality of electrically alterable andelectrically interrogatable bistable memory means each storing a binaryone or a binary zero signal, each said memory means having an inputcircuit means for receiving an interrogation signal and an outputcircuit means for carrying a said binary signal in response to thereceipt of an interrogation signal; interrogation means for applyinginterrogation signals to said plurality of memory means so that when asaid memory means is interrogated the output circuit means of saidmemory means carries a binary signal representative of the binary signalstored in said bistable memory means, said interrogating means having aninput circuit means for receiving input pulse signals and a plurality ofoutput circuit means, one coupled to each said memory means, forrespectively carrying a said interrogation signal in accordance with thenumber of received input pulse signals; and circuit means connected tosaid output circuit means of said plurality of memory means and adaptedto be connected to a load; each bistable memory means being of thenondestructive readout, dual plate type comprising an easily polarizedmemory plate and a permanently polarized drive plate, the plates havingfacing surfaces which are secured to each other.
 27. Apparatus as setforth in claim 26 wherein said interrogating means includes circuitmeans for sequentially energizing its output circuit means in accordancewith the number of received input pulse signals to thereby sequentiallyapply interrogating signals to said plurality of memory means. 28.Apparatus as set forth in claim 27 including a source of time spacedpulses; and, said interrogation means being coupled to said pulse sourcefor interrogating the next succeeding of said plurality of memory meansin the response to the receipt of said pulse.
 29. Apparatus as set forthin claim 26 wherein each said bistable memory means includes:ferroelectric storage capacitor memory plate means having a surface,said plate means adapted to be polarized in one of two stable states;and, piezoelectric driving plate means having a portion thereof securedto at least a portion of said surface in such a manner that applicationof a said interrogation signal to said driving plate means causestransmission of mechanical forces to said memory plate means indirections acting both laterally and perpendicularly of said surface sothat said memory plate means provides an output voltage signal oF apolarity in accordance with the state of polarization of said memoryplate means.
 30. Apparatus as set forth in claim 26 wherein saidplurality of bistable memory means is a ferroelectric capacitor matrixand includes a plurality of rows each including at least oneferroelectric storage capacitor memory means; and, each of saidplurality of output circuit means of said interrogating meansrespectively carry a said interrogation signal to thereby interrogate aselected row of said ferroelectric storage memory means.
 31. Apparatusas set forth in claim 30 wherein each said row of ferroelectric storagecapacitors includes a plurality of ferroelectric storage memory meanseach corresponding with an associated load; and, circuit means forcoupling each of said plurality of output circuit means of saidinterrogation means to each of said plurality of ferroelectric storagememory means in a said row so that when a said row of memory means isinterrogated the output circuit means of said plurality of memory meanscarry a pattern of binary signals representative of the binary states ofsaid interrogated row of ferroelectric memory means.